ASML designs 1nm process lithography equipment
Source: Science and Technology News
According to foreign media reports, at the ITF (IMEC Technology Forum, .ITF) forum held in Tokyo, Japan, the Belgian semiconductor research institute IMEC, which cooperates with the Dutch semiconductor manufacturer ASML to develop semiconductor lithography machines, officially announced the Relevant technical details at the miniature level.
According to the analysis published by IMEC, ASML has made a clear development plan for the 3nm, 2nm, 1.5nm, 1nm, and even less than 1nm processes, which means that ASML has basically been able to develop the 1nm process. Lithography equipment.
The report pointed out that at the forum, IMEC President and CEO Luc Van den hove emphasized that the process technology will continue to be scaled down to 1 nanometer and below. In this regard, IMEC has also proposed a miniaturization roadmap for the logic component manufacturing process from 3nm, 2nm, 1.5nm, 1nm, and even smaller than 1nm.
According to the introduction of TSMC and Samsung Electronics, the major wafer manufacturers, starting from the 7nm process technology, some process technologies have introduced EUV lithography equipment with NA=0.33, and the 5nm process technology has also achieved a frequency increase, but for the 2nm process technology In the future, ultra-fine process technology will still require lithography equipment that can achieve higher recognition rates and higher NA (NA=0.55).
In this regard, ASML has also completed the basic design of high NA EUV lithography equipment as the NXE:5000 series, but the commercialization time is expected to be around 2022 at the earliest. However, this next-generation lithography equipment will become very huge due to its huge optical system.
In fact, in the past, it has been working closely with IMEC to develop semiconductor lithography technology, but in order to develop and use high NA EUV lithography equipment, ASML established a new "IMEC-ASML High NA EUV" laboratory in the IMEC campus to achieve a common Develop and develop related technologies using high NA EUV lithography equipment. In addition, the company also plans to cooperate with material suppliers to further develop photomasks and photoresists.
Van den hove also pointed out that the purpose of shrinking the logic component process technology is to reduce power consumption, improve performance, reduce area, and reduce costs, which is commonly referred to as PPAC. In addition to these four goals, as the process moves to 3 nanometers, 2 nanometers, 1.5 nanometers, and even surpasses 1 nanometers to reach processes below 1 nanometers, we will strive to achieve sustainable development of microprocessor process technology to meet the needs of The demand for the application of advanced technology in the future.
According to foreign media reports, at the ITF (IMEC Technology Forum, .ITF) forum held in Tokyo, Japan, the Belgian semiconductor research institute IMEC, which cooperates with the Dutch semiconductor manufacturer ASML to develop semiconductor lithography machines, officially announced the Relevant technical details at the miniature level.
According to the analysis published by IMEC, ASML has made a clear development plan for the 3nm, 2nm, 1.5nm, 1nm, and even less than 1nm processes, which means that ASML has basically been able to develop the 1nm process. Lithography equipment.
The report pointed out that at the forum, IMEC President and CEO Luc Van den hove emphasized that the process technology will continue to be scaled down to 1 nanometer and below. In this regard, IMEC has also proposed a miniaturization roadmap for the logic component manufacturing process from 3nm, 2nm, 1.5nm, 1nm, and even smaller than 1nm.
According to the introduction of TSMC and Samsung Electronics, the major wafer manufacturers, starting from the 7nm process technology, some process technologies have introduced EUV lithography equipment with NA=0.33, and the 5nm process technology has also achieved a frequency increase, but for the 2nm process technology In the future, ultra-fine process technology will still require lithography equipment that can achieve higher recognition rates and higher NA (NA=0.55).
In this regard, ASML has also completed the basic design of high NA EUV lithography equipment as the NXE:5000 series, but the commercialization time is expected to be around 2022 at the earliest. However, this next-generation lithography equipment will become very huge due to its huge optical system.
In fact, in the past, it has been working closely with IMEC to develop semiconductor lithography technology, but in order to develop and use high NA EUV lithography equipment, ASML established a new "IMEC-ASML High NA EUV" laboratory in the IMEC campus to achieve a common Develop and develop related technologies using high NA EUV lithography equipment. In addition, the company also plans to cooperate with material suppliers to further develop photomasks and photoresists.
Van den hove also pointed out that the purpose of shrinking the logic component process technology is to reduce power consumption, improve performance, reduce area, and reduce costs, which is commonly referred to as PPAC. In addition to these four goals, as the process moves to 3 nanometers, 2 nanometers, 1.5 nanometers, and even surpasses 1 nanometers to reach processes below 1 nanometers, we will strive to achieve sustainable development of microprocessor process technology to meet the needs of The demand for the application of advanced technology in the future.